Operating long on-chip buses

ABSTRACT

As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

The present invention relates to operating long on-chip buses.

Integrating large system on chip (SOC) devices can be a great challengeas the environment on the chip becomes more and more noisy. At the sametime as the technology shrinks, on-chip wires are becoming narrower anddenser, and their RC time constants are increasing. This leads toworsening delay over long interconnect runs. Such delays call fortechniques which will enable on-chip buses to run at highest possiblespeed allowed by the environment.

Typically, inverters or buffers are used as receivers at the receivingend of a bus. FIG. 1 of the accompanying drawings schematicallyillustrates a bus on an integrated circuit device, the bus including aseries of bus lines 4 which are interconnecting wires between drivers 2and receivers 6. Each bus line 4 connects a driver 2 to a correspondingreceiver 6. Since the rise/fall times are typically excessively long(for example, see FIG. 2 of the accompanying drawings; “IN” refers toinput to bus driver and “LINEOUT” refers to output at the end of a 10 mmlong bus on Metal 2 CMOS12) at the receiving end, the speed of sensingtransitions on the bus is very slow, if the switching threshold of theinverter/buffer receiver is at Vdd/2 (half the supply voltage).

It is proposed to change this threshold (lower/raise) for both therising and falling edge transitions so as to achieve fast sensing aswell as achieve robust signaling in noisy environment. Changing thethresholds may cause the receiver to sense glitches caused by crosstalk,which are highly undesirable. In the case of very noisy environment thethreshold can be raised above Vdd/2. Thus there exists a possibility tovary threshold of the receiver in order to achieve robust signaling atthe highest possible speed in that environment.

Schmitt triggers are often used for rejecting noise wherein hysteresisof the transfer characteristics is utilized to raise the threshold forrising transitions and vice-versa for falling transitions at its input.However, this only provides variation of threshold in one direction andcannot be calibrated. In the proposed scheme the threshold can be variedin both the directions (raise or lower from Vdd/2 point) to suit theconditions on the chip. Since the calibration is done on the chip ittakes care of process variations on both the front-end processing aswell as on the backend processing.

According to one aspect of the present invention, there is provided abus system for an integrated circuit device, the bus comprising aplurality of bus lines (4) each of which connects a driver circuit (2)and a receiver circuit (6), characterized in that each receiver circuitcomprises:

-   -   a first detector (10) operably connected to receive a data        signal from an associated bus line (4), and operable to detect a        rising transition of the data signal with respect to a first        threshold level, and to produce a first output signal upon        detection of such a rising transition;    -   a second detector (12) operably connected to receive the data        signal, and operable to detect a falling transition of the data        signal with respect to a second threshold level, and to produce        a second output signal upon detection of such a transition; and    -   output means operable to output the first or second output        signal as a receiver output signal.

According to another aspect of the present invention, there is provideda method of operating a bus system for an integrated circuit device, thebus comprising a plurality of bus lines (4) each of which connects adriver circuit (2) and a receiver circuit (6), characterized in that themethod comprises:

-   -   receiving a data signal from a bus line (4);    -   detecting a rising or falling transition of the data signal with        respect to first and second threshold levels respectively;    -   producing a first output signal upon detection of a rising        transition, or producing a second output signal upon detection        of a falling transition; and    -   outputting the first or second output signal as a receiver        output signal.

FIG. 1 illustrates schematically a bus on an integrated circuit device;

FIG. 2 illustrates RC response at the receiving end of a 10 mm wire onan M2, 0.13 μm CMOS circuit;

FIG. 3 illustrates a receiver circuit;

FIG. 4 illustrates the receiver circuit of FIG. 3 in more detail;

FIG. 5 illustrates a scheme with a dummy bus;

FIG. 6 illustrates a scheme which uses the same bus for calibration;

FIG. 7 illustrates a state diagram for the calibration circuit;

FIG. 8 illustrates glitch detection by using convention latches;

FIG. 9 illustrates some of the simulation waveforms.

FIG. 3 illustrates a receiver circuit for use in embodiments of thepresent invention. The receiver of FIG. 3 has first and second detectors10 and 12. The first detector 10 is sensitive to transitions occurringfrom low to high and the second detector from high to low. Bothdetectors are connected to receive the data signal transmitted on thebus wire 4, and are operable to detect respective transitions of thatsignal on the bus wire 4. The detectors have respective outputs whichare combined via a multiplexer 14. The multiplexer 14 has a select linecontrolled by the previous data on the bus wire 4. The previous datavalue is stored in a state element 16. A state element could be aflip-flop, latch or a delay line.

The thresholds of the first and second detectors of the receiver arecontrolled by a control word, which is generated by a calibrator (notshown in FIG. 3).

The receiver circuit is shown in more detail in FIG. 4. It consists oftwo inverters whose thresholds can be controlled independently by thecalibrator. The calibrator applies the control word, which selects thenumber of transistors T10, T12 to be used in parallel in a respectivepull down/up networks in the inverters of the receiver. This tunes thethreshold of the inverters for rising and falling transitionsrespectively. The selection of signal to be output from the multiplexeris based on the previous value of the output, which is stored in thestate element 16. For example, if the present value is high then themultiplexer 14 selects the output of the detector (inverter) 12 which issensitive to falling transitions.

The calibrator 18 uses either a dummy bus as shown in FIG. 5, or themain bus with slight modifications in the driver circuit (which thenuses a multiplexer) as shown in FIG. 6, to simulate worst case switchingconditions on the chip. The simulation enables the calibrator to set thecontrol word to an appropriate value. The calibration can be done onceduring power-up or during chip initialization. The dummy bus 20technique shown in FIG. 5 involves the use of an extra set of busdrivers 22, bus lines 24, and bus receivers 26 to simulate the crosstalk to be executed on the real bus 2,4,6.

The calibrator circuit is preferably implemented as a finite statemachine (shown in FIG. 7), which applies signals on primary bus wires(aggressor wires) and measures the crosstalk on at least one secondarybus wire (victim wire). If a glitch is detected which can possibly causefailure then it changes the threshold of the receiver 10, 12 andre-applies the signals to the primary bus wires. This procedure isrepeated until the output of the receiver circuit.

A glitch sensor circuit 28, which includes a pair of latches, is used tocapture the glitches. See FIG. 8. The first latch 30, is transparent lowand is connected to ‘b’ in FIG. 4. The other latch 32 is transparenthigh and is connected to ‘a’ in FIG. 4. Output from one of the latch isselected by a multiplexer 34 based on the logic level on the victim wireM which is generated by the calibrator 18.

FIG. 7 illustrates the state diagram of the calibrator, ‘M’ and ‘S’represent the signals on victim and aggressor wires respectively.Calibration starts when ‘Ca’ is asserted. ‘T’ is the reset signal to theglitch capturing latches. ‘C’ is a signal which goes high whenever thelatches detect appreciable glitch at their inputs. ‘CW1’ and ‘CW2’ arethe signals which are used to increment a counter in the calibrator 18that generates the control word for the receiver circuit thresholdadaptation.

As the calibration proceeds it can be seen with reference to FIG. 9 thatthe thresholds of the receiving inverters are adjusted so that theamplitude of glitches decrease.

The simulations are performed on a 10 mm long bus at minimum spacing andminimum width on Metal 2 in CMOS12 TSMC technology. In a typical processcase, 10% performance gain can be achieved for the bus structurespecified above. On the other hand in a very noisy environment which mayoccur due to process variations the threshold may be raised by thecalibrator and hence avoid glitches at the output of receiver. In thiscase penalty will have to be paid in terms of increase in worst casedelay along the bus. Glitch prevention may be very essential at theoutput of the receiver, especially in asynchronous circuits.

1. A bus system for an integrated circuit device, the bus comprising aplurality of bus lines each of which connects a driver circuit and areceiver circuit; and a glitch sensor circuit which is operable todetect glitches on at least one of the bus lines, characterized in thateach receiver circuit comprises: a first detector operably connected toreceive a data signal from an associated bus line, and operable todetect a rising transition of the data signal with respect to a firstthreshold level, and to produce a first output signal upon detection ofsuch a rising transition; a second detector operably connected toreceive the data signal, and operable to detect a falling transition ofthe data signal with respect to a second threshold level, and to producea second output signal upon detection of such a transition; output meansoperable to output the first or second output signal as a receiveroutput signal; and wherein the first and second threshold levels arevariable.
 2. A bus system as claimed in claim 1, wherein the outputmeans comprises a multiplexer operably connected to receive the firstand second output signals, and operable to output the receiver outputsignal in dependence upon a previous receiver output signal.
 3. A bussystem as claimed in claim 1, further comprising a calibrator foradjusting the first and second threshold levels.
 4. A bus system asclaimed in claim 3, wherein the first and second detectors includerespective pluralities of transistors, and the calibrator is operable toactivate varying numbers of those transistors, in order to adjust thethreshold levels.
 5. A bus system as claimed in claim 3, wherein theglitch sensor circuit comprises a pair of latches each having an output,and a multiplexer operable to select one of the latch outputs for supplyto the calibrator.
 6. A bus system as claimed in claim 3, wherein thecalibrator is operable to supply test signals to the bus lines, and theglitch sensor circuit is operable to detect glitches on at least one busline and to supply a glitch signal to the calibrator, the calibratorthen being operable to adjust the threshold values of the detectors independence upon the glitch signal.
 7. A bus system as claimed in claim3, further comprising a test bus including a plurality of test drivers,and corresponding pluralities of bus lines and receivers, the calibratorbeing operable to supply test signals to the test bus lines, and theglitch sensor circuit being operable to detect glitches on the test buslines and to supply a glitch signal to the calibrator, the calibratorthen being operable to adjust the threshold values of the detectors independence upon the glitch signal.
 8. A method of operating a bus systemfor an integrated circuit device, the bus comprising a plurality of buslines each of which connects a driver circuit and a receiver circuit,characterized in that the method comprises: receiving a data signal froma bus line; detecting a rising or falling transition of the data signalwith respect to first and second threshold levels respectively, whereinthe first and second threshold levels are variable; producing a firstoutput signal upon detection of a rising transition, or producing asecond output signal upon detection of a falling transition; outputtingthe first or second output signal as a receiver output signal; anddetecting glitches on at least one of the bus lines.
 9. A method asclaimed in claim 8, wherein the first or second output signal is outputby a multiplexer operably connected to receive the first and secondoutput signals, and operable to output the receiver output signal independence upon a previous receiver output signal.
 10. A method asclaimed in claim 8, further comprising adjusting the first and secondthreshold levels.
 11. A method as claimed in claim 10, wherein therising transition is detected by a first detector and the fallingtransition is detected by a second detector, the first and seconddetectors include respective pluralities of transistors, and thethreshold levels are adjusted by activating varying numbers of thosetransistors.
 12. A method as claimed in claim 8, wherein the glitchesare sensed using a glitch sensor circuit which comprises a pair oflatches each having an output, and a multiplexer operable to select oneof the latches.
 13. A method as claimed in claim 8, further comprisingsupplying test signals to the bus lines, detecting glitches on at leastone bus line, and adjusting the threshold values in dependence upon thedetected glitches.
 14. A method as claimed in claim 8, furthercomprising supplying test signals to test bus lines, detecting glitcheson the test bus lines, and adjusting the threshold values in dependenceupon the detected glitches.
 15. A bus system as claimed in claim 1,wherein the glitches are signals on one of the bus lines caused bycrosstalk from data signals on the other bus lines, the glitches causingtransitions to be detected by at least one of the first and seconddetectors associated with the one of the bus lines.
 16. A method asclaimed in claim 8, wherein the glitches are signals on one of the buslines caused by crosstalk from data signals on the other bus lines, theglitches causing transitions to be detected by at least one of the firstand second detectors associated with the one of the bus lines.